1. Field of the Invention
This invention concerns an integrated circuit and the design method thereof, and specifically concerns an integrated circuit with clock skew suppressed and the design method for realizing this suppression.
2. Description of Related Art
Logical integrated circuits are formed by combining basic logic circuits such as AND circuits, OR circuits, and flip flops. Generally, the logic circuits within an integrated circuit are designed to operate according to the timing given by one type of clock signal. This arrangement is used to provide reliable execution of operations such as data input and output between integrated circuits and external circuits and data sending and transmission between each part of circuits installed within an integrated circuit according to a fixed sequence.
With the design of integrated circuits, suppression of clock skew is vital. Clock skew means causing a dispersion in delay time of clock signals that reach each basic logic circuit and causing phase difference in these clock signals. For integrated circuit design, when determining placement of basic logic circuits or a routing pattern for clock signals, etc., mechanisms are employed to suppress the occurrence of clock skew.
Generally, with integrated circuits, multiple driver circuits for clock signals are installed. To each clock driver is connected one or multiple basic logic circuits. As a design method for suppressing the generation of clock skew in this case, we can list methods such as making the wiring length or wiring width of the integrated circuit clock input terminal and each clock driver the same, or making each clock driver drive capacity the same.
However, even if the wiring length, wiring width, or drive capacity are made the same, when there is a different number of basic logic components connected to each clock driver, it is impossible to completely suppress the generation of clock skew. This is because the size of the load of the clock driver differs according to the number of basic logic components connected to the clock driver. This load size depends on items such as the total value of parasitic resistance due to the wiring from each clock driver to each basic logic circuit, the total value of the parasitic capacitance of this wiring, and the total value of the input impedance of each basic logic circuit. Then, to change the delay time of clock signals according to the load size, clock skew is generated between clock drivers.
Clock skew generated due to such reasons becomes a cause of faulty operation of integrated circuits. Especially in recent years, the operating speed demanded for integrated circuits is accelerating, so suppressing the clock skew generated due to dispersion of driver circuit loads is an important task.